以下为12比特的有符号截掉低7比特取高五比特后四舍五入的verilog函数形式

function signed [4:0] round_7;
  input signed [11:0] din  ;
  reg carrry_bit ;
  begin
    if ( din[11:7] == 5'b0_1111 ) begin  //正数最大值，无法进位
      carrry_bit = 0 ;
    end else if ( (din[11] == 0) ) begin  //数值为正
      carrry_bit = din[6] ;
    end else begin
      carrry_bit = ( din[6] & (|din[5:0]) ) ; // 数值为负
    end
    round_7 = {   din[11:7] }     + carrry_bit     ;
  end 
endfunction