Before using the L1 caches, you must invalidate the instructioncache, the data cache, and the BTAC.
It is not required to invalidate the main TLB, even though it is recommended for safety reasons. This
ensures compatibility with future revisions of the processor. Steps to initialize L1 Caches:
1. Invalidate TLBs:
mcr p15, 0, r0, c8, c7, 0 (r0 = 0)
2. Invalidate I-Cache:
mcr p15, 0, r0, c7, c5, 0 (r0 = 0)
3. Invalidate Branch Predictor Array:
mcr p15, 0, r0, c7, c5, 6 (r0 = 0)
4. Invalidate D-Cache:
mcr p15, 0, r11, c7, c14, 2 (shouldbe done for all the sets/ways)
5. Initialize MMU.
6. Enable I-Cache and D-Cache:
mcr p15, 0, r0, c1, c0, 0 (r0 = 0x1004)
7. Synchronization barriers:
dsb (Allows MMU to start)
isb (Flushes pre-fetch buffer)
