VHDL实现如下:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTIDY Trans38 IS
PORT(
A:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Trans38;
ARCHITECTURE behav OF trans38 IS
BEGIN
WITH A SELECT
Y<= "00000000" SLL CONV_INTEGER(A) when "0001",
"00000000" SLL CONV_INTEGER(A) when "001" , --有效输出为高电平
"00000000" SLL CONV_INTEGER(A) when "010" ,
"00000000" SLL CONV_INTEGER(A) when "011" ,
"00000000" SLL CONV_INTEGER(A) when "100" ,
"00000000" SLL CONV_INTEGER(A) when "101" ,
"00000000" SLL CONV_INTEGER(A) when "110" ,
"00000000" SLL CONV_INTEGER(A) when "111" ;
END behav;
注：来自互联网，未经实机测试，谨慎使用；
