(materials covered in UWM ECE551)
Lecture 01 Part I
Description Phase:
- Specification
- Planning : data path, control signals, states machines, bubble diagram
- Design Entry : Verilog
- Functional Test
- Synthesis : go in to synthesis tool with constraints(timing info, input arrive relating to clock edge? - static time analysis), how gates interconnected.
- Post-Synthesis Test : run the test bench against netlist from synthesis(test and/or/nor gates)
- APR, Parasitic Extraction & Timing Checks
- Manufacture & Hardware Validation
HDL : Hardware Description Language (Verilog / Sverilog, VHDL) - ASCII text
Synthesis : Takes a description of what a circuit does and creates the hardware to do it
Hardware Implementations:
- Full Custom (Manual VLSI( - drawing schematics all by yourself))
- Semi-Custom (Standard Cell (- standard cell libraries and interconnected with metal, take more time), Gate Array( - chips with gates before connecting them with layers, function depends on how you interconnect the metal layers))
- Programmable/Configurable (FPGA (- what we do, configurable, configure into SRAM, expansive, power hungry), PLD( - smaller, configure to non-volatile memory(NVM) like flash))
Hardware building blocks : transistors -> switches -> gates -> circuits
Standard Cell - library of common gates and structures(cells) , arrange the cells on the chip and connect them using metal wiring
FPGA - "Programmable hardware", use small memories as truth tables of functions, connect blocks using programmable routing
Netlist: a ASCII text representation of the interconnect of a schematic( we use Structural Verilog Netlist)
Lecture 01 Part II
Verilog basis - How to declare a module?(图1&2)
Or declare in this way:
-where you put the [x:x] matters , which is declare a vector is before the name, and an array is after
Wrong declaration: input sel [1:0];
This is array of single bit scalar(2 1-bit wide signals), not a 2bits vector(single 2-bit wide signal).
Proper declaration: input [1:0] sel;
However, bit selection of a vector dose occur after the signal name(图3)
Type wire - net type used for anything driven that is purely combinational implementation (no flops), example below:
wire [15:0] product;
assign product = A * B; //hardware multiplier, where A and B are two inputs
Type reg - any signal assigned to in an always block(flop or maybe also a combinational implementation) had to be declared as type reg. Example below:
reg [15:0] product;
always @(posedge clk)
product <= A*B;
Type logic - superset of reg and wire.（used for combinational or flops）. Signal assigned to in an always block had to be declared as type reg or logic. Example below:
output logic [15:0] result //set to type logic
output [15:0] result //set to default type wire
Module Coding Styles:
1.Structural - connect primitives and modules
2.Dataflow - use continuous assignments
3.Behavioral - use initial and always blocks
We will go in depth to Structural:
- Building hierarchy
- Synthesis tools output structural verilog
Primitives:
- No declarations - can only be instantiated
- output port appears before input ports
- and, or, nand, nor, xor
- file name of file containing the module can have a different name to the module, but recommend file and module have the same name
Examples:
and N25 (Z,A,B,C); //name specified
and #10 (Z,A,B,C),(X,C,D,E); //delay specified, two and gate with delay
and #10 N30 (Z,A,B,C); //name and delay
Other examples:
module majority (major, V1, V2, V3);
...
endmodule //instantiate a module majority ourselves
majority iCO(.V1(A), .V2(B), .V3(Ci), .major(Co)); // positional or connect by reference, strongly recommend connect by reference, which is ".<port name>(<signal name>)"
// when a port is not connect to a signal, that port is high impedance, current consumption. if intentionally not using it .<port name>(). leave it empty
Let's look at a 8-bit ripple carry adder(图4):
Tri-States:
Lecture 01 Part III
Finite State Machine
- Mealy FSM(results can be depend on not only current state, but also current input) and Moore (only depends on current state
Let's see a Single Slope A2D Converter below:
- essentially comparing the analog input at the "+" terminal to the analog input at the "-", and output a digital result. If analog input at "+" is greater than at "-", then gt output 1.(图7-State: cnv)
But we want to take 8 samples of analog input at "+" terminal, accumulate it and divide by 8(take the average to get a more accurate result), thus we have the part below - state:accum (图8):
Why result is just the 10 bits?
- That's because "dividing by 8" is just shift right 3 bits, which is taking the last 10 bits.
Sample counter: count up to 8, and compare to see if it finish the adding process.
Bubble Diagram:
One small bug : "inc_smpl". smp_eq_8 signal is using a 3 bits register to store values and to compare to see if it finish, but it's actually allowing the FSM to accumulate up to the 7th times(starts at 1, ends at 7). Thus, we could either use a 4 bits accumulator, or instead let inc_smpl count up after state accum, beside "clr_dac"(Thus we starts counting from 0 to 7)
Lecture 02 Part I
Flipflop:
The flipflop sustains the signal value by the two inverters at E = 0. At E = 1, weak in the inverter at the bottom allows the enable signal to pass the new input D into the flipflop.
not inv1(Q,n1);
not(weak0,weak1) inv2(n1,Q);
Meta-stability is when signal input D changes while Enable signal E is also changing. Whenever we have asynchronous signal coming in the circuit, we double flop it before using them.(like below)
Numbers in Verilog:
General format is: <size>'<base><number>
examples: 4'b1101 // 4-bit binary number equal to 13
10'h2e7 // 10-bit wide number specified in hex
Numbers can have x or z as values
-x = unknown(uninitialized or in contention), z = High Impedance(not driven or not connected, would output unknown)
12'h13x //12-bit number with lower four bits unknown 00010011xxxx
-If size is not specified then it depends on simulator/machine. (in some create 32-bit register when you only need like 5 bits)
-Support negative number as well
- Use _n at the end of a signal to indicate active low, rst_n = 1'b0 // assert reset
Signal strength level:
supply(strongest, like a supply VDD) > strong(default) > pull(pull up device) > weak(sustainer, leaker) > highz(high impedance)
reg(or logic, superset of reg and wire) are storage nodes:
-retain their value till a new value is assigned
-do not need a driver, unlike (a net) wire
-can be changed in simulation by assigning new value
-anything assigned in an always or initial block must be assigned to a signal of type reg(or logic)
Vectors:
- a collection of bits
- logic [15:0] src1_bus;
- Bus is not equal to Vector
Concatenation by Replication {N{sig}}
-a digit N can be placed in front of a set of { } to replicate scalar or vector quantity is inside the curly braces
-can be used for sign extension
- {2'b00,{3{2'b10}},2'b11} = 10'b0010101011
assign signedDiv8 = (value>>>3);
-Verilog default to unsigned
- this does not do arithmetic shift right until value and signedDiv8 is declared as type signed
Lecture 02 Part II
Dataflow Verilog
- generic form of assign: assign [drive_strength][delay] list_of_net_assignments;
- and gate functionality
assign out = a&b;
- 32-bit adder:
wire [31:0] sum, src1, src2; // three 32 bit wide vector
assign {c_out, sum} = src1 + src2 + c_in; // producing 32 bit sum, the extra bit goes into the c_out
-Multiply-accumulate unit:
assign {overflow, Z} = A*B + C; //output Z [31:0],output overflow, input[15:0]A,B, input[31:0] C
- Conditional Operator
-2:1 Mux
assign out = conditional_expr ? true_expr : false_expr;
-use localparam to make code more readable
-use enum type
Reduction operators:
-reduction AND
-reduction OR
-reduction XOR
Lecture 02 Part III
Parameter:
The $clog2 function returns the ceiling of the logarithm to the base 2.
In Verilog, if not specified assign, it will declare a single bit wide wire type, so good habit: before module, do:
`default_nettype none
Parent cannot access "internal" signals of child(synthesis tool does not allow that), if you need a signal, must make a port.
Lecture 03
-Delays are useful for Simulation only(testbench level), Synthesis tool ignores timing control, only timing controlled is on clock-cycle basis
-Types of Delay:
-Inertial Delay(Gates)
-Transport Delay(Nets)
-PVT corners
-Min/Typ/Max
-different timing sets: and #(1:2:3) g1(out,a,b); //1 ns min, 2ns typical, 3ms max delay
-and #(2:3:4, 1:2:3) g1(out,a,b) //gate has different rise, fall for min:typ:max
Design Flow
-DUT Verilog code + Testbenches -> Verilog simulator
-Synth script (constraint the design, how fast to run, operating condition) -> Synthesis(cell library)
-gate level struct(instances of and, or, nor, etc) -> gate level netlist -> Verilog Simulator(modelsim)
-APR(auto placement and route) ->SDF Files(final timing check) + layout
Output Test Info
-$strobe is safer to use than $display, because it outputs when the changed list is empty and ready to advance time
Generating Clocks
-initial clk =0;
always
#5 clk = ~clk;
Exhaustive Testing(for small block) - test all possible values
Force/Release In Testbenches
- force the DUT into error situation to see what it does
Behavioral Verilog
Initial Statement
-initial and always form basis of all behavioral Verilog
-initial and always cannot be nested
-initial statement start at time 0 and execute once
-useful for testbenches, but they don't synthesize(not in DUT)
Always statement
-operates continuously
-can use a trigger list to control operation; @(a,b,c)
-in absence of a trigger list, it re-evaluate when the last <LeftHandStatement> assignment completes
Flipflops
-negedge is on the transitions
- 1->x,z,0
- x,z->0
-posedge
- 0->x,z,1
- x,z->1
Lecture 04
All flop have asynchronous reset. in this case, rst_n should be in the sensitivity list of the flop.
scan flops used for testing if there is a bad transistor in industry manufacturing.
gated clock: remove the clk signal from flop to reduce dissipating power.
In standard verilog anything assigned inside an always block must be of type reg, but in system verilog it could also be type logic.
Non-blocking Assignment(used for sequential logic): in flipflop, non-blocking assignment updated simultaneously multiple assignment if no delays given, parallel transferring the input.
Blocking Assignment(used for combinational logic): Whereas blocking assignment works like software, won't do the next assignment until the last Right Hand Side get the result
Non-Blocking and blocking should not be mixed in the same always block
The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does.
Vector fill token: preset the vector with whatever length to all 1's
reg [WIDTH-1:0] timer;
timer = `1;
always_comb block use for combinational logic, and it can self-infer the sensitivity list without us specifying it.
In the example of comparing a and b, and setting a_graterthan_b, a_lessthan_b,a_equalto_b, default values of variables(graterthan=0,lessthan=0,equalto=0)when making a combinational logic circuit part, or the synthesis will think it is a latch, then do "hold value(maintaining)" when it's not assigned to a new one.
Verilog default to unsigned magnitude
Lecture 05
Case Statements
- will be able to detect x and z
- casez & casex used x,z,? as wild cards in both case item & case expression, error prone
- case () inside uses x,z,? as don't care bit in case items only
- unique means one and only one case will match, infer that it can synthesize it flat structure, no priority -> mux
- priority tells the synthesizer and simulator that at least one of the cases of the cases will always match, it's ok to not state all the possibilities
- if I don't have a power of 2 states, I should add a default state(generally IDEL state or a state which has clear path going back to the IDLE state) to the case statement
- unless flops have the same conditions under which they are reset and enabled, separate them into different always flop
Lecture 06
We are using Synopsys 32nm educational library in this class
Synthesis priorities
- functionality(synthesized netlist same as coded in verilog?)
- design rules(fanout, transition times, hot electron)
- performance criteria(speed,power,area)
Synthesis is cost function derive
- function of timing, area, power, in this priority order, can be changed
constraint
(input delay+ input to flipflop D delays+ set up time) < cycle time
-Timing constraint
-example: create_clock -name "clk" -period 20 -waveform { 0 10 } clk
-drive strength of input（ input output slope creates RC problem, how strong/weak the gate drive in the inputs(R), how big the capacitance, the bigger the longer the slope be(C). RC time constant determine the slope. C is known, R is not)
- set_driving_cell -lib_cell <cell> -library <lib> <list_of_inputs>
- set_drive <# of ohms> <signal>
-Capacitive loading affects the propagation delay of a gate(output of the gate)
- set_load <capacitance> <list of outputs>
-parasitic capacitance of this node(capacitance created by any electronic elements separated by insulator in the circuit)
- set_wire_load_model -name <m_name> -library <lib_name>
- Hot Electron Effect(too many electron stuck at the gate oxide, cause VT degradation), solution: limit operating time at high VDS& VGS
- set_max_transition_time <time> [current_design]
Writing Synopsis scripts and run
- unix_prompt>design_vision –shell dc_shell
