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Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.
构建一个从 0 到 15（含）计数的 4 位二进制计数器，周期为 16。复位输入是同步的，应将计数器复位为 0。
image.png
module top_module (
input clk,
input reset, // Synchronous active-high reset 同步高电平有效
output [3:0] q);
always @(posedge clk)
if (reset)
q <= 4'd0;
else
q <= q + 4'd1;
endmodule
---------------------------官网答案-------------------------------
module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= q+1; // Because q is 4 bits, it rolls over from 15 -> 0.
// If you want a counter that counts a range different from 0 to (2^n)-1,
// then you need to add another rule to reset q to 0 when roll-over should occur.
endmodule
- Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.
构建一个从 0 到 9（含）计数的十进制计数器，周期为 10。复位输入是同步的，应将计数器复位为 0。
我的思路是想着把10，11，12，13，14，15的输入信号为不是所需信号，都将其置为0
但是结合官网所给的参考答案，好像自己的解题思路好像还是不太对，因为这是计数器，将9置为0之后就重新开始了，根本没办法有10产生啊。哎！
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
reg[3:0] i;
always@(posedge clk)
if(reset)
q <= 0;
else if(q > 4'd8 )
q <= 0;
else
q <= q + 1 ;
endmodule
-------------------------官网解答-------------------------------------------
module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset || q == 9) // Count to 10 requires rolling over 9->0 instead of the more natural 15->0
q <= 0;
else
q <= q+1;
endmodule
- Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.
制作一个从 1 到 10 的十位计数器，包括 1 到 10。复位输入是同步的，应将计数器复位为 1。
module top_module (
input clk,
input reset,
output [3:0] q);
always@(posedge clk)
if(reset || q == 4'd10)
q <= 4'd1;
else
q <= q + 1;
endmodule
-------------------------------官网答案------------------------------------
无
-
Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.
构建一个从 0 到 9 计数的十进制计数器，周期为 10。复位输入是同步的，应该将计数器复位为 0。我们希望能够暂停计数器，而不是总是在每个时钟周期递增，所以slowena输入指示计数器何时应该增加。
image.png
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always@(posedge clk)
if(reset)
q <= 4'd0;
else if(slowena) begin
if(q == 9)
q <= 4'd0;
else
q <= q + 1;
end
endmodule
这里需要知道引入了slowena的输入信号，只有当这个信号有效时计数器才会执行计数增加的功能，这也就是为什么要将q==9的代码写在if(slowena)代码块中，就是这个原因了
Design a 1-12 counter with the following inputs and outputs:
ResetSynchronous active-high reset that forces the counter to 1EnableSet high for the counter to runClkPositive edge-triggered clock inputQ[3:0]The output of the counterc_enable,c_load,c_d[3:0]Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:the 4-bit binary counter (
count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). Thecount4module is provided to you. Instantiate it in your circuit.logic gates
module count4(
input clk,
input enable,
input load,
input [3:0] d,
output reg [3:0] Q
);
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter's enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.
设计一个具有以下输入和输出的 1-12 计数器：
复位同步高电平有效复位，强制计数器为 1
启用设置高以使计数器运行
Clk正边沿触发时钟输入
Q[3:0]计数器的输出
c_enable, c_load, c_d[3:0]控制信号进入提供的 4 位计数器，因此可以验证正确的操作。
您有以下可用组件：
下面的 4 位二进制计数器 ( count4 )，它具有启用和同步并行加载输入（加载的优先级高于启用）。count4模块提供给您。在你的电路中实例化它。
逻辑门如上
c_enable 、c_load和c_d输出是分别进入内部计数器的enable、load和d输入的信号。它们的目的是允许检查这些信号的正确性。
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable; // 提供使能
assign c_load = reset | ((Q == 4'd12) & enable) ; // 对count 4进行复位操作
assign c_d = 1'h1; // 给与复位初始值
count4 the_couter(.clk(clk),.enable(c_enable),.load(c_load),.Q(Q),.d(c_d));
endmodule
- From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).
从 1000 Hz 时钟导出一个称为OneHertz的 1 Hz 信号，该信号可用于驱动一组小时/分钟/秒计数器的启用信号以创建数字挂钟。由于我们希望时钟每秒计数一次，因此OneHertz信号必须每秒准确地断言一个周期。使用模 10 (BCD) 计数器和尽可能少的其他门构建分频器。还要从您使用的每个 BCD 计数器输出使能信号（c_enable[0] 为最快的计数器，c_enable[2] 为最慢的）。
好吧，这一题说实话，属实为难我了。真心没看懂！
参考Troke博主的解题思路：
题目分析：题目希望我们用1000hz的时钟来输出一个1hz的信号（即1000的分频器），同时将输出使能信号也进行输出，这实际上还是一个计数的问题。题目中给了我们一个模10的bcd计数器，(即计数从0到9计数)我们可以通过例化这个模块来实现输出1hz信号，具体思路就是将1000按位进行分解，由于是从000开始，所以只需要计数到999时，输出就能达成目标。所以可以将1000分解成个位、十位、百位、千位，然后每个位按一定条件进行0-9的循环计数，下面用时序图来描述下整个大概的流程
————————————————
版权声明：本文为CSDN博主「Troke」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/weixin_45931009/article/details/118912900
/*我的解答*/
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
);
wire [3:0] Q0,Q1,Q2; //定义个位，十位，百位上的数
bcdcount counter0 (clk, reset, c_enable[0],Q0); //个位
bcdcount counter1 (clk, reset, c_enable[1],Q1); //十位
bcdcount counter2 (clk, reset, c_enable[2],Q2); //百位
//使用组合逻辑
always @(*) begin
if(reset == 1'b1)
c_enable <= 3'b001; //先让个位上的数进行0-9的计数
else begin
if(Q0 == 4'd9) begin //当个位上的数计数到9时
c_enable <= 3'b011; //让十位上也开始计数
if(Q1 == 4'd9) begin //当十位上的数也计数到9时
c_enable <= 3'b111; //让百位上也开始计数
end
end
else
c_enable <= 3'b001;
end
end
always @(*) begin
if(reset == 1'b1)
OneHertz = 1'b0;
else if(Q0 == 4'd9 && Q1 == 4'd9 && Q2 == 4'd9) //满足三个位上都为9时，直接输出
OneHertz = 1'b1;
else
OneHertz = 1'b0;
end
endmodule
