1.an'zhuang

https://wenku.baidu.com/view/6e7c665f7375a417866f8fb8.html
http://www.swarthmore.edu/NatSci/echeeve1/Ref/embedRes/QQS_V/QuickQuartusVerilog.html

2.ISP:实时在线编程模式。
3.warn:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.

 Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

4.ERRO:cannot launch the modelsim-altera software because you did not specify the path...

http://blog.csdn.net/jack2010666/article/details/16940341

5.Quartus 提示did not specify an EDA simulation tool

https://zhidao.baidu.com/question/1925429049436192667.html

6.You selected ModelSim as Simulation Software in EDA Tool Settings, however NativeLink found ModelSim-Altera in the path -- correct path or change EDA Tool Settings and try again.
Check the NativeLink log file C:/intelFPGA_lite/all_qua/Vhdl3_nativelink_simulation.rpt for detailed error messages

该工程设置的[仿真](http://bbs.elecfans.com/zhuti_proteus_1.html)工具名称与在QuartusII软件中指定的该软件路径不匹配。
http://bbs.elecfans.com/jishu_541049_1_1.html

7.Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance：
···
8.Error: Top-level design entity " " is undefined：

verilog文件（.v）里的模块名和顶层实体名(Top-level design entity，一般就是.v文件的文件名)不一致。