1. 参考：https://electronics.stackexchange.com/questions/134595/what-does-the-subthreshold-swing-of-a-mosfet-actually-mean
Subthreshold swing is also the inverse of the subthreshold slope. On a graph of Ids(Vgs) with logarithmic (base 10) axis for Ids the subthreshold slope is found as the straight-line approximation of the subthreshold current, normally expressed in units of decades/mV. Subthreshold swing is expressed in units of mV/decade. Both express the same, however subthreshold swing is more often used.
Are these two interpretations same but for the former case device is in strong inversion and the latter case the device is in weak inversion ?
When subthreshold swing is calculate and quoted it is usual that only the magnitude of the subthreshold swing is of interest, so the sign from the slope is removed. Both cases are for weak inversion (=subthreshold)
What i understood is to have large change in the output current low gate voltage should be enough which implies sub threshold swing should be smaller. If this is true then how are tunneling FETs better over the conventional MOSFETs.(where in tunneling FETs we say the sub threhold swing is not limited?)
Subthreshold swing should normally be minimized when it is allowed by the application. Small subthreshold swing means better channel control, e.g. improved Ion/Ioff, which usually means less leakage, and less energy. For subthreshold circuits it also means better performance. Silicon MOSFETs have a theoretical minimum subthreshold swing of about 60mV/decade for room temperature. FETs using tunneling in some manner can achieve much better (I have seen 5mV/decade quoted), how is another story altogether and I suppose they are not without problems, otherwise what are they waiting for?
2. 百度百科
亚阈值摆幅（Subthreshold swing）， 又称为 S因子。这是MOSFET在亚阈状态工作时、用作为逻辑开关时的一个重要参数，它定义为：
S = dVgs / d(log10 Id)，单位是[mV/dec]。S在数值上就等于为使漏极电流Id变化一个数量级时所需要的栅极电压增量ΔVgs，注意S是从Vg-Id曲线上的最大斜率处提取出来的。表示着Id~Vgs关系曲线的上升率。
S值与器件结构和温度等有关：衬底反向偏压将使表面耗尽层电容CD减小，则S值减小；界面陷阱的存在将增加一个与CD并联的陷阱容，使S值增大；温度升高时，S值也将增大。为了提高MOSFET的亚阈区工作速度，就要求S值越小越好，为此应当对MOSFET加上一定的衬偏电压和减小界面陷阱。
室温条件下（T=300k），MOS型器件 S的理论最小值为log(10)*KT/q=59.6mV/dec≈60 mV/dec，但一些新型器件，如隧穿器件（TunnelingTransistor），可以获得低于此理论值的亚阈值摆幅。
在大规模数字集成电路的缩小规则中， 恒定电压缩小规则、 恒定电场缩小规则等都不能减小S值，所以这些缩小规则都不适用，只有采用半经验的恒定亚阈特性缩小规则才比较合理。
