实验目的

• 掌握组合逻辑电路的基本分析和设计方法

• 理解半加器和全加器的工作原理并掌握利用全加器构成不同字长加法器的各种方法

• 学会元件例化的方式进行硬件电路设计

• 学会利用软件仿真实现对数字电路的逻辑功能进行验证和分析

实验内容

• 设计实现逐次进位加法器,进行软件仿真并在实验平台上测试

• 设计实现超前进位加法器,进行软件仿真并在实验平台上测试

• 使用VHDL自带的加法运算实现一个4位加法器

实验源代码

• 逐次进位加法器
  Library IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.STD_LOGIC_UNSIGNED.ALL;

      entity add3 is
        port 
       (
        a   : in std_logic_vector(3 downto 0);
        b   : in std_logic_vector(3 downto 0);
        ci  : in std_logic;
        s   : out std_logic_vector(3 downto 0); 
        co  : out std_logic);
       end add3;
  
       architecture rtl of add3 is
       signal  c0,c1,c2,c3 : std_logic;
  
       begin
       s(0) <= (a(0) xor b(0)) xor (not ci);
        c1 <= ((not ci) and a(0)) or ((not ci) and b(0)) or(a(0) and b(0));
  
       s(1) <= a(1) xor b(1) xor c1;
       c2 <= (c1 and a(1)) or (c1 and b(1)) or (a(1) and b(1));
  
       s(2) <= a(2) xor b(2) xor c2;
      c3 <= (c2 and a(2)) or (c2 and b(2)) or (a(2) and b(2));
  
      s(3) <= a(3) xor b(3) xor c3;
      co <= (c3 and a(3)) or (c3 and b(3)) or (a(3) and b(3));
         end rtl;
  

• 超前进位加法器

     LIBRARY IEEE;
     USE IEEE.STD_LOGIC_1164.ALL;
     USE IEEE.STD_LOGIC_ARITH.ALL;
     ENTITY adder1 IS
     PORT(
       a1,a2,a3,a4,b1,b2,b3,b4,c0:IN STD_LOGIC;
       s1,s2,s3,s4,c4:OUT STD_LOGIC
     );
     END adder1;
  
    ARCHITECTURE behav OF adder1 IS
    BEGIN
    PROCESS(a1,a2,a3,a4,b1,b2,b3,b4,c0)
    VARIABLE c1,c2,c3:STD_LOGIC;
    BEGIN
       s1<=(a1 xor b1)xor (not c0);
       c1:=(a1 AND b1)OR((a1 OR b1)AND (not c0));
      s2<=(a2 xor b2)xor c1;
      c2:=(a2 AND b2)OR((a2 OR b2)AND a1 and b1)or ((a2 or b2)and(a1 or b1)and (not c0));
     s3<=(a3 xor b3) xor c2;
     c3:=(a3 and b3)or((a3 or b3)and a2 and b2)or((a3 or b3)and(a2 or b2)and a1 and b1)
  or((a3 or b3)and(a2 or b2)and(a1 or b1)and (not c0));
     s4<=(a4 xor b4) xor c3;
     c4<=((a4 xor b4)and(a3 xor b3)and(a2 xor b2)and(a1 xor b1)and (not c0))
   or((a4 xor b4)and(a3 xor b3)and(a2 xor b2)and a1 and b1 )
   or((a4 xor b4)and(a3 xor b3)and a2 and b2 )
    or ((a4 xor b4)and a3 and b3) 
    or (a4 and b4);
    END PROCESS;
    END behav;
  

• VHDL自带加法运算实现加法器

  library IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity add is
      port 
       (
       a   : in std_logic_vector(3 downto 0);
       b   : in std_logic_vector(3 downto 0);
       ci  : in std_logic;
       s   : out std_logic_vector(3 downto 0); 
       co  : out std_logic);
      end add;
  
      architecture rtl of add is
      signal sint:std_logic_vector(4 downto 0);
      signal aa,bb:std_logic_vector(4 downto 0);
  
   begin
  
   aa<='0'&a;
   bb<='0'&b;
   sint<= aa+bb+ci;
   s(3 downto 0) <= sint(3 downto 0);
   co <= sint(4);
   end rtl;