什么是make?
make是用来简化程序编译的Unix工具。而Makefile可以看作make的配置文件。make通过从Makefile读取一系列的规则，包含的头文件，链接哪些库，哪些文件需要先编译，哪些文件需要后编译，哪些文件需要重新编译，甚至于进行更复杂的功能操作。
如何使用make
配置好Makefile文件之后，每当有新修改的时候，重新运行make指令就可以重新编译可执行文件。每次有新的模块加入工程的时候就需要在makefile中添加新的规则来编译新的模块。
# 编译整个工程
make
# 编译Makefile中的特定target
make target_label
# 清除Makefile文件定义的rm 命令
make clean
创建Makefile文件
- 一般规则, make命令执行的入口是target
target: dependency1 dependency2 ...
<tab> command
# for example
program: program.o mylib.o
gcc -o program program.o mylib.o
例如有make 和 make clean 规则的Makefile
# -g for adding debug info
# -Wall turns on most, but not all compiler warnings
all: myprog.c
gcc -g -Wall -o myprog myprog.c
clean:
$(RM) myprog
- 更加复杂的Makefile文件
指定编译器
编译选项
# the compiler: gcc for C program, define as g++ for C++
CC = gcc
# compiler flags:
# -g adds debugging information to the executable file
# -Wall turns on most, but not all, compiler warnings
CFLAGS = -g -Wall
# the build target executable:
TARGET = myprog
all: $(TARGET)
$(TARGET): $(TARGET).c
$(CC) $(CFLAGS) -o $(TARGET) $(TARGET).c
clean:
$(RM) $(TARGET)
更加复杂Makefile例子
# This is an example Makefile for a countwords program. This
# program uses both the scanner module and a counter module.
# Typing 'make' or 'make count' will create the executable file.
#
# define some Makefile variables for the compiler and compiler flags
# to use Makefile variables later in the Makefile: $(<var_name>)
#
# -g adds debugging information to the executable file
# -Wall turns on most, but not all, compiler warnings
#
# for C++ define CC = g++
CC = gcc
CFLAGS = -g -Wall
# typing 'make' will invoke the first target entry in the file
# (in this case the default target entry)
# you can name this target entry anything, but "default" or "all"
# are the most commonly used names by convention
#
default: count
# To create the executable file count we need the object files
# countwords.o, counter.o, and scanner.o:
#
count: countwords.o counter.o scanner.o
$(CC) $(CFLAGS) -o count countwords.o counter.o scanner.o
# To create the object file countwords.o, we need the source
# files countwords.c, scanner.h, and counter.h:
#
countwords.o: countwords.c scanner.h counter.h
$(CC) $(CFLAGS) -c countwords.c
# To create the object file counter.o, we need the source files
# counter.c and counter.h:
#
counter.o: counter.c counter.h
$(CC) $(CFLAGS) -c counter.c
# To create the object file scanner.o, we need the source files
# scanner.c and scanner.h:
#
scanner.o: scanner.c scanner.h
$(CC) $(CFLAGS) -c scanner.c
# To start over from scratch, type 'make clean'. This
# removes the executable file, as well as old .o object
# files and *~ backup files:
#
clean:
$(RM) count *.o *~
- 带有链接文件，包含头文件库文件的Makefile
-I 指定header 文件路径
-L 指定library 文件路径
-l+库名称 指定需要链接的库
# 'make depend' uses makedepend to automatically generate dependencies
# (dependencies are added to end of Makefile)
# 'make' build executable file 'mycc'
# 'make clean' removes all .o and executable files
#
# define the C compiler to use
CC = gcc
# define any compile-time flags
CFLAGS = -Wall -g
# define any directories containing header files other than /usr/include
#
INCLUDES = -I/home/newhall/include -I../include
# define library paths in addition to /usr/lib
# if I wanted to include libraries not in /usr/lib I'd specify
# their path using -Lpath, something like:
LFLAGS = -L/home/newhall/lib -L../lib
# define any libraries to link into executable:
# if I want to link in libraries (libx.so or libx.a) I use the -llibname
# option, something like (this will link in libmylib.so and libm.so:
LIBS = -lmylib -lm
# define the C source files
SRCS = emitter.c error.c init.c lexer.c main.c symbol.c parser.c
# define the C object files
#
# This uses Suffix Replacement within a macro:
# $(name:string1=string2)
# For each word in 'name' replace 'string1' with 'string2'
# Below we are replacing the suffix .c of all words in the macro SRCS
# with the .o suffix
#
OBJS = $(SRCS:.c=.o)
# define the executable file
MAIN = mycc
#
# The following part of the makefile is generic; it can be used to
# build any executable just by changing the definitions above and by
# deleting dependencies appended to the file from 'make depend'
#
.PHONY: depend clean
all: $(MAIN)
@echo Simple compiler named mycc has been compiled
$(MAIN): $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
# this is a suffix replacement rule for building .o's from .c's
# it uses automatic variables $<: the name of the prerequisite of
# the rule(a .c file) and $@: the name of the target of the rule (a .o file)
# (see the gnu make manual section about automatic variables)
.c.o:
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@
clean:
$(RM) *.o *~ $(MAIN)
depend: $(SRCS)
makedepend $(INCLUDES) $^
# DO NOT DELETE THIS LINE -- make depend needs it
