- Introduction to the IIC bus protocol
1.1 IIC::Integrated circuit bus, is a synchronous serial half-duplex communication bus.
1.2 IIC bus structure: 1. It is composed of clock line SCL and data line SDA, and both are connected to resistors to ensure that the bus idle state is high. 2. The bus supports multi-device linking, allowing many hosts to exist, and each device has a unique address 3. The number of connections to the bus is limited by the maximum capacity of the bus of 400pf.
1.3 IIC protocol: three signals: start signal, stop signal, and response signal. Two notes: data validity, data transfer order. 3. One state: idle state.
1.4 IIC protocol timing: Start signal: When SCL is high flat, SDA changes from high flat to low. Stop signal: When SCL is high, SDA changes from low to high. Acknowledgment signal: SDA is high by default under the influence of pull-up resistor, and slave pulling SDA low is to confirm the receipt of data ACK. (Data is sent high first) - Introduction of AT24C02
EEPROM is a memory that does not lose data after power failure, and is commonly used to store some configuration information, which can be loaded when the system is powered back on. The AT24C02 is a 2Kbit EEPROM memory that uses IIC communication. - AT24C02 read and write timing
Write operation: AT24C02 supports byte write mode and page write mode. Byte write mode is that one address and one data are written. Page write mode is to write data continuously. Only one address needs to be written, and the address will increase itself when continuously writing data, but there is a page limit, and when it exceeds one page, the data exceeds the original written data. But reading requires automatic page turning.
Read operation: AT24C02 supports current address read mode, random address read mode and sequential read mode. - IIC configuration steps
4.1 Enable the corresponding clocks of SCL and SDA.
4.2Set the GPIO working mode.
4.3Write basic signals.
4.4Write read and write functions.
4.5 The SDA pin of the IIC should be used as both output and output, so the open-drain output is used. When output, the host outputs 0, which can pull the signal low to achieve low-level transmission. When input, the host sets the output 1 state, which is equivalent to releasing the SDA pin, at which time the external device can actively pull the SDA pin low or release.
Introduction to the IIC
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