第一章 FPGA改善时序方法

在FPGA设计中，可以从以下五个方面来改善设计的时序表现

1. 增加寄存器层级

   增加寄存器层级，即在关键路径上，通过插入中间寄存器的方法来对关键路径进行切割。该方法适用于对延时不敏感的设计中。

   module fir(
       output   [7:0]   Y,
       input    [7:0]   A, B, C, X,
       input            clk,
       input validsample);
       
       reg [7:0] X1, X2, Y;
       
       always @(posedge clk)
           if(validsample) begin
               X1 <= X;
               X2 <= X1;
               Y <= A* X+B* X1+C* X2;
            end
       
   endmodule
   

   优化后：

   module fir(
       output [7:0] Y,
       input [7:0] A, B, C, X,
       input clk,
       input validsample);
       
       reg [7:0] X1, X2, Y;
       reg [7:0] prod1, prod2, prod3;
       
       always @ (posedge clk) begin
           if(validsample) begin
               X1 <= X;
               X2 <= X1;
               prod1 <= A * X;
               prod2 <= B * X1;
               prod3 <= C * X2;
           end
               Y <= prod1 + prod2 + prod3;
       end
       
   endmodule
   

   对应RTL为：

   
   
   image.png

   和

   
   
   image.png

2. 结构并行化

   结构并行化策略指的是，通过将关键路径上的较大的逻辑结构进行重组，使用较小的并行结构进行实现。这种方法适用于一些满足条件（可并行实现）的串行结构。

   X = {A, B}
   X * X = {A, B} * {A, B} = {(A * A), (2 * A * B), (B * B)};
   

   可优化为：

   module power3(
       output [7:0] XPower,
       input [7:0] X,
       input clk);
       
       reg [7:0] XPower1;
       // partial product registers
       reg [3:0] XPower2_ppAA, XPower2_ppAB, XPower2_ppBB;
       reg [3:0] XPower3_ppAA, XPower3_ppAB, XPower3_ppBB;
       reg [7:0] X1, X2;
       wire [7:0] XPower2;
       
       // nibbles for partial products (A is MS nibble, B is LS
       nibble)
       wire [3:0] XPower1_A = XPower1[7:4];
       wire [3:0] XPower1_B = XPower1[3:0];
       wire [3:0] X1_A = X1[7:4];
       wire [3:0] X1_B = X1[3:0];
       wire [3:0] XPower2_A = XPower2[7:4];
       wire [3:0] XPower2_B = XPower2[3:0];
       wire [3:0] X2_A = X2[7:4];
       wire [3:0] X2_B = X2[3:0];
       
       // assemble partial products
       assign XPower2 = (XPower2_ppAA << 8)+(2*XPower2_ppAB << 4)+XPower2_ppBB;
       assign XPower = (XPower3_ppAA << 8)+(2*XPower3_ppAB << 4)+XPower3_ppBB;
       
       always @(posedge clk) begin
           // Pipeline stage 1
           X1 <= X;
           XPower1 <= X;
           // Pipeline stage 2
           X2 <= X1;
           // create partial products
           XPower2_ppAA <= XPower1_A * X1_A;
           XPower2_ppAB <= XPower1_A * X1_B;
           XPower2_ppBB <= XPower1_B * X1_B;
           // Pipeline stage 3
           // create partial products
           XPower3_ppAA <= XPower2_A * X2_A;
           XPower3_ppAB <= XPower2_A * X2_B;
           XPower3_ppBB <= XPower2_B * X2_B;
       end
       
   endmodule
   
   

   对应RLT图为

   
   
   image.png

3. 逻辑结构平行化

   所谓了逻辑结构平行化，即取消一下不必要的优先级链级结构，这跟第2点有点类似。通俗的讲，多用case，少用if else。

   module regwrite(
       output reg [3:0] rout,
       input clk, in,
       input [3:0] ctrl);
       
       always @(posedge clk)
           if(ctrl[0]) 
               rout[0] <= in;
           else if(ctrl[1]) 
               rout[1] <= in;
           else if(ctrl[2]) 
               rout[2] <= in;
           else if(ctrl[3]) 
               rout[3] <= in;
   endmodule
   

   可优化为：

   module regwrite(
       output reg [3:0] rout,
       input clk, in,
       input [3:0] ctrl);
       
       always @(posedge clk) begin
           if(ctrl[0]) 
            rout[0] <= in;
           if(ctrl[1]) 
            rout[1] <= in;
           if(ctrl[2]) 
            rout[2] <= in;
           if(ctrl[3]) 
            rout[3] <= in;
       end
       
   endmodule
   

   对应RTL为：

   
   
   image.png
   
   

   与

   
   
   image.png

4. 寄存器平衡

   寄存器平衡，就是将关键路径上各个寄存器之间的逻辑重新进行划分，从而使得每级寄存器之间的逻辑延时达到均衡。

   module adder(
       output reg [7:0] Sum,
       input [7:0] A, B, C,
       input clk);
       
       reg [7:0] rA, rB, rC;
       
       always @(posedge clk) begin
           rA <= A;
           rB <= B;
           rC <= C;
           Sum <= rA + rB + rC;
       end
   endmodule
   

   优化后

   module adder(
       output reg [7:0] Sum,
       input [7:0] A, B, C,
       input clk);
       
       reg [7:0] rABSum, rC;
       
       always @(posedge clk) begin
           rABSum <= A + B;
           rC <= C;
           Sum <= rABSum + rC;
       end
   endmodule
   

   对应RLT图为：

   
   
   image.png
   
   

   与

   
   
   image.png

5. 路径重配置

   路径重配置策略，即将关键逻辑上的一些逻辑运算转移到相邻的路径上去。

   module randomlogic(
       output reg [7:0] Out,
       input [7:0] A, B, C,
       input clk,
       input Cond1, Cond2);
       
       always @(posedge clk)
           if(Cond1)
            Out <= A;
           else if(Cond2 && (C < 8))
            Out <= B;
           else
            Out <= C;
   endmodule
   

   可优化为：

   module randomlogic(
       output reg [7:0] Out,
       input [7:0] A, B, C,
       input clk,
       input Cond1, Cond2);
       
       wire CondB = (Cond2 & !Cond1);
       
       always @(posedge clk)
           if(CondB && (C < 8))
            Out <= B;
           else if(Cond1)
            Out <= A;
           else
            Out <= C;
   endmodule
   

   对应RTL图为

   
   
   image.png
   
   

   和

   
   
   image.png