How to use "for" statement to facilitate coding with System Verilog

Author: monokent

Example 1

Below is two simple examples.

integer j;
always@(posedge clk)
begin
    if (!rst_n) begin
        for (j=1; j<=6; j++) 
            p1_real[j] <= 0;
    end
    else begin

genvar i;
for (i=3; i<=6; i++) begin
    assign p2_real_tr[i] =p2_real[i][wDataInOut+14-1 : 14];
    assign p2_imag_tr[i] =p2_imag[i][wDataInOut+14-1 : 14];
end

Note the difference between integer and genvar.

In both case above, the 6 in for sentence can be replaced by a parameter which may be delivered from high level module.